求助：MSP430F5438A芯片，XT2时钟采用外部有源24MHz时钟，UCS和P5.2口应该如何设置？我的总是出现XT2OFFG置位的情况，MCLK选用的是DCO的输出，切换不到XT2。

MSP430F5438A芯片，XT2时钟采用外部有源24MHz时钟，UCS和P5.2口应该如何设置？我的总是出现XT2OFFG置位的情况，MCLK选用的是DCO的输出，切换不到XT2。我的代码里，先把内核电压提升到LEVEL 3，然后设置P5.2口为输入引脚、特殊功能引脚；设置XT2为BYPASS模式，XT2 OFF。最后面的循环通不过，发现是XT2OFFG始终置位。具体代码如下：

//set Vcore to level 3

........

//P5.0=NONE(output); P5.1=NONE(output); P5.2=XT2IN(input); P5.3=NONE(output); P5.4=LOCK(IO output); P5.5=UA1STE(IO output); P5.6=UA1SIMO(output); P5.7=UA1SOMI(input);
P5DIR = BIT8_ALL_OUTPUT & BIT8_2_INPUT & BIT8_7_INPUT;
P5DS = RESET_8BITS;
//P5REN = SET_8BITS;
P5SEL = BIT8_2_SELPMF + BIT8_6_SELPMF + BIT8_7_SELPMF;

UCSCTL6 = XT2DRIVE_2 + XT2BYPASS + XT2OFF + XT1DRIVE_0 + XT1OFF;
UCSCTL5 = DIVM__1 + DIVS__1 + DIVA_SEL + DIVPA__32;

//ACLK is from REFOCLK; SMCLK is from XT2CLK.
UCSCTL4 = SELA__REFOCLK + SELS__XT2CLK + SELM__XT2CLK;

UCSCTL1 = DCORSEL_2 + DISMOD;

UCSCTL8 = MCLKREQEN + MODOSCREQEN;

//Shut down FLL
_bis_SR_register(SCG0 + SCG1);
//Check whether XT2 is fault!!! &// Loop until XT1,XT2 & DCO stabilizes
do
{
UCSCTL7 &= ~(XT2OFFG + XT1HFOFFG + XT1LFOFFG + DCOFFG); // Clear fault flags
SFRIFG1 &= ~OFIFG; // Clear OSC Fault flag
for (TempI = CLK_STB_DELAY; TempI > 0; TempI--) // Time for flag to set
{
;
}
}while ( (SFRIFG1 & OFIFG) );