下面加了很多注释的这两行。这里是IIC430作为主机接收。使能的是接收中断UCB0RXIN。为什么中断向量是USCIAB0TX_VECTOR，而不是USCIAB0RX_VECTOR呢？这里是接收那应该也是USCIAB0RX_VECTOR啊，为什么是TX。求告知。
#include <msp430.h>
unsigned char RXData;
unsigned char RXCompare;
int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1OUT &= ~BIT0; // P1.0 = 0
P1DIR |= BIT0; // P1.0 output
P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x048; // Slave Address is 048h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
IE2 |= UCB0RXIE; // //////////////////////////////////////////////////////////////////////////////////
RXCompare = 0; // Used to check incoming data
while (1)
{
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTXSTT; // I2C start condition
while (UCB0CTL1 & UCTXSTT); // Start condition sent?
UCB0CTL1 |= UCTXSTP; // I2C stop condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
if (RXData != RXCompare) // Trap CPU if wrong
{
P1OUT |= BIT0; // P1.0 = 1
while (1); // Trap CPU
}
RXCompare++; // Increment correct RX value
}
}
// USCI_B0 Data ISR
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
{
RXData = UCB0RXBUF; // Get RX data
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}