这是一个电压值的测量程序的一部分。
开发板是MSP4305529LP。
下面的程序只有SPI通信和ADC两个功能。
我发现该程序不能进入ADC中断。
而如果不进行SPI通信，则ADC正常。
下列代码中，
把main函数中
UCA0TXBUF = 0xaa;
while(UCA0STAT & UCBUSY);
取消注释，则程序不会进入ADC中断的服务程序，而是会进入isr_trap.asm文件中的
JMP __TI_ISR_TRAP
而把那两行代码注释掉，即不进行SPI通信，则采样中断正常。
请问这是为什么呢？该怎样解决呢？
谢谢！
#include <msp430.h>
#define Num_of_Results 8
volatile unsigned int results[Num_of_Results];
void init_ADC(void)
{
P6SEL |= 0x01; // Enable A/D channel A0
ADC12CTL0 = ADC12ON+ADC12SHT0_8+ADC12MSC; // Turn on ADC12, set sampling time
// set multiple sample conversion
ADC12CTL1 = ADC12SHP+ADC12CONSEQ_2; // Use sampling timer, set mode
ADC12IE = 0x01; // Enable ADC12IFG.0
ADC12CTL0 |= ADC12ENC; // Enable conversions
ADC12CTL0 |= ADC12SC; // Start conversion
}
void init_spi(void)
{
P3SEL |= BIT3+BIT4; // P3.3,4 option select
P2SEL |= BIT7; // P2.7 option select
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTL = 0; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
}
int main(void)
{
init_ADC();
init_spi();
UCA0TXBUF = 0xaa;
while(UCA0STAT & UCBUSY);
__bis_SR_register(GIE); // Enable interrupts
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12ISR (void)
#else
#error Compiler not supported!
#endif
{
static unsigned char index = 0;
switch(__even_in_range(ADC12IV,34))
{
case 0: break; // Vector 0: No interrupt
case 2: break; // Vector 2: ADC overflow
case 4: break; // Vector 4: ADC timing overflow
case 6: // Vector 6: ADC12IFG0
results[index] = ADC12MEM0; // Move results
index++; // Increment results index, modulo; Set Breakpoint1 here
if (index == Num_of_Results)
{
index = 0;
}
case 8: break; // Vector 8: ADC12IFG1
case 10: break; // Vector 10: ADC12IFG2
case 12: break; // Vector 12: ADC12IFG3
case 14: break; // Vector 14: ADC12IFG4
case 16: break; // Vector 16: ADC12IFG5
case 18: break; // Vector 18: ADC12IFG6
case 20: break; // Vector 20: ADC12IFG7
case 22: break; // Vector 22: ADC12IFG8
case 24: break; // Vector 24: ADC12IFG9
case 26: break; // Vector 26: ADC12IFG10
case 28: break; // Vector 28: ADC12IFG11
case 30: break; // Vector 30: ADC12IFG12
case 32: break; // Vector 32: ADC12IFG13
case 34: break; // Vector 34: ADC12IFG14
default: break;
}
}